This invention relates to frequency synthesis techniques that employ a phase locked loop, and more particularly relates to techniques for modulating a phase locked loop frequency synthesizer.
Modern communication transmitters traditionally employ a phase locked loop for frequency synthesis of a communication carrier signal modulated with transmission data. The phase locked loop enables the carrier signal frequency to be precisely controlled and accordingly enables the data on which the carrier signal modulation is based to be reliably transmitted at a stable, known frequency. In such a phase locked loop (PLL) frequency synthesizer, a voltage controlled oscillator (VCO) produces the output carrier signal at the desired frequency based on a VCO frequency control signal. In a simplified PLL configuration, this control is achieved by a feedback loop, with the VCO output signal coupled via the feedback loop to a phase-frequency detector which compares the VCO signal phase or frequency to that of a fixed-frequency reference signal and produces a frequency control signal corresponding to the phase difference between the VCO signal and the fixed-frequency signal. This frequency control signal is smoothed by a low pass loop filter and then applied to the VCO such that in its steady state the VCO output signal frequency matches that of the fixed-frequency reference signal.
Typically, a frequency divider is included in the PLL feedback loop to enable division of the frequency of the VCO output signal to a frequency that is a multiple of that of a fixed-frequency reference source. The output of the frequency divider is compared by the phase-frequency detector to the fixed-frequency source for controlling the VCO phase. In this way, the frequency of a carrier signal produced by the VCO is constantly controlled such that it is "phase locked" to a multiple of that of the fixed-frequency reference.
There exist a wide range of techniques for modulating a PLL-synthesized carrier signal. In a first general class of such techniques, hereinafter referred to as direct open-loop modulation, a modulation data stream is directly applied to the VCO, or to an appropriate node in the PLL that enables access to the VCO, for a time period during which the PLL feedback loop is broken, for adjusting the VCO frequency control signal to account for the modulation In this direct open-loop PLL modulation scenario, the PLL sets the carrier frequency during times that modulation is not performed, to control carrier frequency accuracy. But the required break in the PLL feedback loop during modulation limits this modulation technique to only burst mode communication because the PLL feedback must be periodically closed to permit this carrier frequency realignment by the closed PLL feedback. This modulation technique is further limited in that while the loop is open, great care must be taken to achieve high isolation of the VCO input from undesirable perturbations, and the leakage current must be minimized to achieve a desirable level of drift.
There has been proposed a second general class of PLL modulation that overcomes many of the limitations of a direct open-loop PLL modulation technique. In this second class, hereinafter referred to as closed-loop modulation, a modulation data stream is directly applied to the VCO or a node in the PLL enabling access to the VCO, or is indirectly applied to the PLL by way of the PLL frequency divider, in either case without breaking the PLL feedback loop, for adjusting the VCO frequency control signal to account for the modulation. For example, Washburn, in U.S. Pat. No. 4,242,649; Vandegraaf, in U.S. Pat. No. 4,864,257; and Mutz, in U.S. Pat. No. 5,130,676; all describe closed-loop PLL modulation techniques in which a modulation signal is directly applied to the VCO frequency control signal in a closed feedback loop for modulating the VCO output signal. Riley, in U.S. Pat. No. 4,965,531; Hietala et al., in U.S. Pat. No. 5,055,802; and Shepherd et al., in U.S. Pat. No. 4,994,768; describe application of a digital modulation data stream to a closed-loop PLL frequency divider for modulating the divide value of the divider and thus the PLL.
Direct or indirect closed-loop PLL modulation is recognized to be primarily limited in that the frequency response of a given PLL imposes a bandwidth constraint on modulation data to be applied to the PLL in a closed-loop configuration. For example, the bandwidth of closed-loop direct modulation to the VCO is impacted by the high pass nature of the PLL components effecting the VCO, while the bandwidth of both closed-loop indirect modulation and closed-loop direct modulation at a point ahead of the low pass filter are impacted by the low pass nature of this filter. In this second scenario, the bandwidth, and corresponding data rate, of the modulation data stream must be of the same order or less than the bandwidth of the PLL, in its basic configuration, to enable the PLL dynamics to fully accommodate the data stream, i.e., to ensure that the data stream is not attenuated by the characteristic low pass nature of the transfer function of the PLL. But while a PLL is typically characterized by a bandwidth up to about the kilohertz range, many communications applications require a modulation data stream bandwidth in the megahertz range.
In an effort to mitigate this bandwidth discrepancy, there have been proposed various modulation compensation circuits designed to compensate for relatively low PLL bandwidth and enable wider bandwidth closed-loop PLL modulation. For example, Washburn, in U.S. Pat. No. 4,242,649; Druker, in U.S. Pat. No. 4,313,209; and Vandegraaf, in U.S. Pat. No. 4,864,257; describe analog operational amplifier circuits designed for use in direct closed-loop PLL modulation techniques to impose on the modulation data an additional transfer function having a frequency response that tends to counter that of the PLL transfer function. Mutz, in U.S. Pat. No. 5,130,676, alternatively proposes generation of an analog compensation signal, based on a given modulation data signal, to be applied to the PLL fixed-frequency reference signal for causing the PLL dynamics to accommodate the modulation data bandwidth.
Like these compensation circuits, the many other techniques proposed for reducing the modulation data-PLL bandwidth discrepancy of closed-loop modulation scenarios generally require additional, specialized analog componentry beyond the PLL componentry, and thus are subject to tolerance variation and are sensitive to process and temperature variations, due to their analog nature. In addition, analog compensation circuits that pre-amplify analog modulation data also amplify undesired noise and thus degrade the PLL performance. The analog compensation circuits also generally require additional power beyond that required of the PLL, and present challenges in producing a PLL system that is entirely integrated. But for many PLL communication applications such operational and manufacturing complications are impractical, due to, e.g., performance, packaging, and power requirements inherent in the application. As a result, strict bandwidth limits must be imposed on the modulation data to be handled by the PLL modulation systems for these applications.